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w25x40bl publication release date: april 21, 2011 - 1- preliminary - revision b 2.5v 4m-bit serial flash memory with 4kb sectors and dual i/o spi
w25x40bl - 2 - table of contents 1. general description .......................................................................................................... 4 2. features .............................................................................................................................. ... 4 3. package types and pin configurations ..................................................................... 5 3.1 pin configuration soic 150 / 208-mil, vsop 150-mil .................................................... 5 3.2 pad configuration wson 6x5-mm, uson 2x3-mm ...................................................... 5 3.3 pin configuration pdip 300-mil ...................................................................................... 6 3.4 pin/pad descriptions ....................................................................................................... 6 4. signal descriptions ........................................................................................................... 7 4.1 chip select (/cs) ............................................................................................................ 7 4.2 serial data input, output and ios (di, do, io0 and io1) ............................................... 7 4.3 write protect (/wp) ......................................................................................................... 7 4.4 hold (/hold) ................................................................................................................ 7 4.5 serial clock (clk) .......................................................................................................... 7 5. block diagram ...................................................................................................................... 8 6. functional descriptions ................................................................................................. 9 6.1 spi operations .......................................................................................................... 9 6.1.1 standard spi instructions ................................................................................................. 9 6.1.2 dual spi instructions ........................................................................................................ 9 6.1.3 hold function ................................................................................................................... 9 6.2 write protection ................................................................................................. 10 6.2.1 write protect features ................................................................................................... 10 7. status register and instructions ............................................................................ 11 7.1 status register .................................................................................................... 11 7.1.1 busy status (busy) ...................................................................................................... 11 7.1.2 write enable latch status (wel) ................................................................................... 11 7.1.3 block protect bits (bp2, bp1, bp0) ................................................................................ 11 7.1.4 top/bottom block protect bit (tb) .................................................................................. 11 7.1.5 reserved bit ................................................................................................................... 11 7.1.6 status register protect (srp) ........................................................................................ 12 7.1.7 status register memory protection ................................................................................ 12 7.2 instructions ........................................................................................................... 13 7.2.1 manufacturer and device identification .......................................................................... 13 7.2.2 instruction set ................................................................................................................. 14 7.2.3 write enable (06h) ......................................................................................................... 15 7.2.4 write enable for volatile status register (50h) .............................................................. 15 7.2.5 write disable (04h) ......................................................................................................... 16 7.2.6 read status register (05h) ............................................................................................ 17 7.2.7 write status register (01h) ............................................................................................ 17
w25x40bl 7.2.8 read data (03h) ............................................................................................................. 19 publication release date: april 21, 2011 - 3 - preliminary - revision b 7.2.9 fast read (0bh) ............................................................................................................. 20 7.2.10 fast read dual output (3bh) ....................................................................................... 21 7.2.11 fast read dual i/o (bbh) ............................................................................................. 22 7.2.12 continuous read mode bits (m7-0) ............................................................................. 24 7.2.13 continuous read mode reset (ffffh) ....................................................................... 24 7.2.14 page program (02h) ..................................................................................................... 25 7.2.15 4kb sector erase (20h) ................................................................................................ 26 7.2.16 32kb block erase (52h) ............................................................................................... 27 7.2.17 64kb block erase (d8h) ............................................................................................... 28 7.2.18 chip erase (c7h or 60h) ............................................................................................... 29 7.2.19 power-down (b9h) ........................................................................................................ 30 7.2.20 release power-down / device id (abh) ....................................................................... 31 7.2.21 read manufacturer / device id (90h) ........................................................................... 33 7.2.22 read manufacturer / device id dual i/o (92h) ............................................................. 34 7.2.23 read unique id number (4bh) ..................................................................................... 35 7.2.24 jedec id (9fh) ............................................................................................................ 36 8. electrical characteristics ......................................................................................... 37 8.1 absolute maximum ratings .......................................................................................... 37 8.2 operating ranges ......................................................................................................... 37 8.3 power-up timing and write inhibit threshold ............................................................... 38 8.4 dc electrical characteristics ........................................................................................ 39 8.5 ac measurement conditions ........................................................................................ 40 8.6 ac electrical characteristics (2.3~3.6v) ....................................................................... 41 8.7 ac electrical characteristics (2.7~3.6v) ....................................................................... 43 8.8 serial output timing ..................................................................................................... 45 8.9 serial input timing ........................................................................................................ 45 8.10 hold timing ................................................................................................................... 45 8.11 write protect timing ..................................................................................................... 45 9. package specification .................................................................................................... 46 9.1 8-pin soic 150-mil (package code sn) ...................................................................... 46 9.2 8-pin vsop 150-mil (package code sv) ..................................................................... 47 9.3 8-pin soic 208-mil (package code ss) ...................................................................... 48 9.4 8-pin pdip 300-mil (package code da) ...................................................................... 49 9.5 8-pad uson 2x3-mm (package code ux) .................................................................. 50 9.6 8-contact 6x5mm wson (package code zp) ............................................................ 51 10. ordering information ..................................................................................................... 53 10.1 valid part numbers and top side marking .................................................................. 54 11. revision history ................................................................................................................ 55
w25x40bl - 4 - 1. general description the w25x40bl (4m-bit) serial flash memories provides a storage solution for systems with limited space, pins and power. the 25x series offers flexibility and performance well beyond ordinary serial flash devices. they are ideal for code download applications as well as storing voice, text and data. the devices operate on a single 2.3v to 3.6v power supply with current consumption as low as 4ma active and 1a for power-down. all devices are offered in space-saving packages. the w25x40bl arrays are organized into 2,048 programmable pages of 256-bytes each. up to 256 bytes can be programmed at a time using the page program instruction. pages can be erased in groups of 16 (4kb sector erase), groups of 128 (32kb block erase), groups of 256 (64kb block erase) or the entire chip (chip erase). the w25x40bl has 128 erasable 4kb sectors and 8 erasable 64kb blocks respectively. the small 4kb sectors allow for greater flexibility in applications that require data and parameter storage. (see figure 2.) the w25x40bl supports the standard serial peripheral interface (spi), and a high performance dual output as well as dual i/o spi: serial clock, chip select, serial data di (i/o0), do (i/o1). spi clock frequencies of up to 50mhz (2.3-3.6v) and 80mhz (2.7-3.6v) are supported allowing equivalent clock rates of 100mhz (2.3-3.6v) and 160mhz (2.7-3.6v) when using the fast read dual i/o instruction. these transfer rates are comparable to those of 8 and 16-bit parallel flash memories. a hold pin, write protect pin and programmable write protect, with top or bottom array control features, provide further control flexibility. additionally, the device supports jedec standard manufacturer and device identification. 2. features ? family of serial flash memories ? w25x40bl: 4m-bit/512k-byte (524,288) ? 256-bytes per programmable page ? uniform 4kb sectors, 32kb & 64kb blocks ? spi with single / dual outputs / dual i/o ? clock, chip select, data i/o, data out ? optional hold function for spi flexibility ? data transfer up to 160m-bits / second ? clock operation to 80mhz ? fast read dual i/o instruction ? auto-increment read capability ? efficient ?continuous read mode? ? low instruction overhead ? continuous read ? as few as 8 clocks to address memory ? allows true xip (execute in place) operation ? software and hardware write protection ? write-protect all or portion of memory ? enable/disable protection with /wp pin ? top or bottom array protection ? volatile & non-volatile status register bits ? flexible architecture with 4kb sectors ? sector erase (4k-byte) ? block erase (32k and 64k-byte) ? page program up to 256 bytes <1ms ? more than 100,000 erase/write cycles ? more than 20-year data retention ? low power consumption, wide temperature range ? single 2.3 to 3.6v supply ? 4ma active current, 1a power-down (typ) ? -40 to +85c operating range ? space efficient packaging ? 8-pin soic 150 / 208-mil, vsop 150-mil ? 8-pad wson 6x5-mm, uson 2x3-mm ? 8-pin pdip 300-mil
w25x40bl publication release date: april 21, 2011 - 5 - preliminary - revision b 3. package types and pin configurations w25x40bl is offered in an 8-pin soic 150-mil or 208-mil (package code sn & ss), an 8-pin vsop 150-mil (package code sv), an 8-pad wson 6x5-mm (package code zp), an 8-pad uson 2x3-mm (package code ux) and an 8-pin pdip 300-mil (package code da) as shown in figure 1a-c respectively. package diagrams and dimensions are illustrated at the end of this datasheet. 3.1 pin configuration soic 150 / 208-mil, vsop 150-mil 1 2 3 4 8 7 6 5 /cs do (io 1 ) /wp gnd top view vcc /hold dio (io 0 ) clk figure 1a. w25x40bl pin assignments, 8-pin soic 150 / 208-mil, vsop 150-mil (package code sn, ss & sv) 3.2 pad configuration wson 6x5-mm, uson 2x3-mm 1 2 3 4 /cs do (io 1 ) /wp gnd vcc /hold dio (io 0 ) clk top view 8 7 6 5 figure 1b. w25x40bl pad assignments, 8-pad wson 6x5-mm, uson 2x3-mm (package code zp & ux)
w25x40bl - 6 - 3.3 pin configuration pdip 300-mil 1 2 3 4 8 7 6 5 /cs do (io 1 ) /wp gnd top view vcc /hold dio (io 0 ) clk figure 1c. w25x40bl pin assignments, 8-pin pdip 300-mil (package code da) 3.4 pin/pad descriptions pin no. pin name i/o function 1 /cs i chip select input 2 do (io1) i/o data input / output 3 /wp i write protect input 4 gnd ground 5 dio (io0) i/o data input / output 6 clk i serial clock input 7 /hold i hold input 8 vcc power supply
w25x40bl publication release date: april 21, 2011 - 7 - preliminary - revision b 4. signal descriptions 4.1 chip select (/cs) the spi chip select (/cs) pin enables and disables device operation. when /cs is high the device is deselected and the serial data output (do) pin is at high impedance. when deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. when /cs is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power-up, /cs must transition from high to low before a new instruction will be accepted. the /cs input must track the vcc supply level at power-up (see ?write protection? and figure 26). if needed a pull-up resister on /cs can be used to accomplish this. 4.2 serial data input, output and ios (di, do, io0 and io1) the w25x40bl supports standard spi and dual spi operation. standard spi instructions use the unidirectional di (input) pin to serially write inst ructions, addresses or data to the device on the rising edge of the serial clock (clk) input pin. standard spi also uses the unidirectional do (output) to read data or status from the device on the falling edge of clk. dual spi instructions use the bidirectional io pins to serially write instructions, addresses or data to the device on the rising edge of clk and read data or status from the device on the falling edge of clk. 4.3 write protect (/wp) the write protect (/wp) pin can be used to prevent the status register from being written. used in conjunction with the status register?s block protect (bp2, bp1 and bp0) bits and status register protect (srp) bit, a portion or the entire memory array can be hardware protected. the /wp pin is active low. 4.4 hold (/hold) the hold (/hold) pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedance and signals on the dio and clk pins will be ignored (don?t care). when /hold is brought high, device operation can resume. the /hold function can be useful when multiple devices are sharing the same spi signals. (?see hold function?) 4.5 serial clock (clk) the spi serial clock input (clk) pin provides t he timing for serial input and output operations. (?see spi operations?)
w25x40bl - 8 - 5. block diagram 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ? ? ? 03ff00h 03ffffh ? block 3 (64kb) ? 030000h 0300ffh 04ff00h 04ffffh ? block 4 (64kb) ? 040000h 0400ffh ? ? ? 07ff00h 07ffffh ? block 7 (64kb) ? 070000h 0700ffh column decode and 256-by te page buf f er beg inning pag e address ending pag e addr ess w25x40bl block segmentation spi command & control logic by te address latch / counter status register write control logic page address latch / counter do (io1) dio (io0) /cs clk /hold /wp high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ? ? ? xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh write protect logic and row decode 01ff00h 01ffffh ? block 1 (64kb) ? 010000h 0100ffh data figure 2. w25x40bl block diagram
w25x40bl publication release date: april 21, 2011 - 9 - preliminary - revision b 6. functional descriptions 6.1 spi operations 6.1.1 standard spi instructions the w25x40bl are accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select (/cs), serial data input (di) and serial data output (do). standard spi instructions use the di input pin to serially write instructions, addresses or data to the device on the rising edge of clk. the do output pin is used to read data or status from the device on the falling edge clk. spi bus operation modes 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 the clk signal is normally low on the falling and rising edges of /cs. for mode 3 the clk signal is normally high on the falling and rising edges of /cs. 6.1.2 dual spi instructions the w25x40bl supports dual spi operation when using the ?fast read dual output (3bh)? and ?fast read dual i/o (bbh)? instructions. these instructions allow data to be transferred to or from the device at two to three times the rate of ordinary serial fl ash devices. the dual spi read instructions are ideal for quickly downloading code to ram upon power-up (code-shadowing) or for executing non-speed- critical code directly from the spi bus (xip). when using dual spi instructions, the di and do pins become bidirectional i/o pins: io0 and io1. 6.1.3 hold function the /hold signal allows the w25x40bl operation to be paused while it is actively selected (when /cs is low). the /hold function may be useful in cases where the spi data and clock signals are shared with other devices. for example, consider if the page buffer was only partially written when a priority interrupt requires use of the spi bus. in this case the /hold function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. to initiate a /hold condition, the device must be selected with /cs low. a /hold condition will activate on the falling edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will terminate after the next falling edge of clk. during a /hold condition, the serial data output (do) is high impedance, and serial data input/output (dio) and serial clock (clk) are ignor ed. the chip select (/cs) signal should be kept active (low) for the full duration of the /hold operation to avoid resetting the internal logic state of the device.
w25x40bl - 10 - 6.2 write protection applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. to address this concern the w25x40bl provides several means to protect data from inadvertent writes. 6.2.1 write protect features ? device resets when vcc is below threshold. ? time delay write disable after power-up. ? write enable/disable instructions. ? automatic write disable after program and erase. ? software write protection using status register. ? hardware write protection using status register and /wp pin. ? write protection using power-down instruction. upon power-up or at power-down the w25x40bl will maintain a reset condition while vcc is below the threshold value of v wi , (see power-up timing and voltage levels and figure 26). while reset, all operations are disabled and no instructions are recognized. during power-up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t puw . this includes the write enable, page program, sector erase, block erase, chip erase and the write status register instructions. note that the chip select pin (/cs) must track the vcc supply level at power-up until the vcc-min level and t vsl time delay is reached. if needed a pull-up resister on /cs can be used to accomplish this. after power-up the device is automatically placed in a write-disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be issued before a page program, sector erase, chip erase or write status register instruction will be accepted. after completing a program, erase or write instruction the write enable latch (wel) is automatically cleared to a write-disabled state of 0. software controlled write protection is facilitated using the write status register instruction and setting the status register protect (srp) and block protect (tb, bp2, bp1 and bp0) bits. these status register bits allow a portion or all of the memory to be configured as read only. used in conjunction with the write protect (/wp) pin, changes to the status register can be enabled or disabled under hardware control. see status register for further information. additionally, the power-down instruction offers an extra level of write protection as all instructions are ignored except for the release power-down instruction.
w25x40bl publication release date: april 21, 2011 - 11 - preliminary - revision b 7. status register and instructions the read status register instruction can be used to provide status on the availability of the flash memory array, if the device is write enabled or disabled, and the state of write protection. the write status register instruction can be used to configure the device write protection features. see figure 3. 7.1 status register 7.1.1 busy status (busy) busy is a read only bit in the status register (s0) that is set to a 1 state when the device is executing a page program, sector erase, block erase, chip erase or write status register instruction. during this time the device will ignore further instructions except for the read status register instruction (see t w , t pp , t se , t be , and t ce in ac characteristics). when the program, erase or write status register instruction has completed, the busy bit will be cleared to a 0 state indicating the device is ready for further instructions. 7.1.2 write enable latch status (wel) write enable latch (wel) is a read only bit in the status register (s1) that is set to a 1 after executing a write enable instruction. the wel status bit is cleared to a 0 when the device is write disabled. a write disable state occurs upon power-up or after any of the following instructions: write disable, page program, sector erase, block erase, chip erase and write status register. 7.1.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, and bp0) are non-volatile read/write bits in the status register (s4, s3, and s2) that provide write protection control and status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instructions (see status register memory protection table). the factory default setting for the block protection bits is 0, none of the array protected. the block protect bits cannot be written to if the status register protect (srp) bit is set to 1 and the write protect (/wp) pin is low. 7.1.4 top/bottom block protect bit (tb) the top/bottom bit (tb) controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection table. the tb bit is non-volatile and the factory default setting is tb=0. the tb bit can be set with the write status register instruction provided that the write enabl e instruction has been issued. the tb bit cannot be written to if the status register protect (srp) bit is set to 1 and the write protect (/wp) pin is low. 7.1.5 reserved bit status register bit location s6 is reserved for future use. current devices will read 0 for this bit location. it is recommended to mask out the reserved bit when testing the status register. doing this will ensure compatibility with future devices.
w25x40bl - 12 - 7.1.6 status register protect (srp) the status register protect (srp) bit is a non-volatile read/write bit in status register (s7) that can be used in conjunction with the write protect (/wp) pin to disable writes to status register. when the srp bit is set to a 0 state (factory default) the /wp pin has no control over status register. when the srp pin is set to a 1, the write status register instru ction is locked out while the /wp pin is low. when the /wp pin is high the write status register instruction is allowed. s7 s6 s5 s4 s3 s2 s1 s0 srp (r) tb bp2 bp1 bp0 wel busy status register protect (non-v olatile) reserved top/bottom protect (non-v olatile) block protect bits (non-v olatile) write enable latch erase/write in progress figure 3. status register bit locations 7.1.7 status register memory protection status register (1) w25x40bl (4m-bit) memory protection tb bp2 bp1 bp0 block(s) addresses density portion x 0 0 0 none no ne none none 0 0 0 1 7 070000h - 07ffffh 64kb upper 1/8 0 0 1 0 6 and 7 060000h - 07 ffffh 128kb upper 1/4 0 0 1 1 4 thru 7 040000h - 07ffffh 256kb upper 1/2 1 0 0 1 0 000000h - 00ffffh 64kb lower 1/8 1 0 1 0 0 and 1 000000h - 01 ffffh 128kb lower 1/4 1 0 1 1 0 thru 3 000000h - 03ffffh 256kb lower 1/2 x 1 x x 0 thru 7 000000h - 07ffffh 512kb all note: x = don?t care
w25x40bl publication release date: april 21, 2011 - 13 - preliminary - revision b 7.2 instructions the instruction set of the w25x40bl consists of nineteen basic instructions that are fully controlled through the spi bus (see instruction set table). instructions are initiated with the falling edge of chip select (/cs). the first byte of data clocked into the dio input provides the instruction code. data on the dio input is sampled on the rising edge of clock with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don?t care), and in some cases, a combination. instructions are completed with the rising edge of edge /cs. clock relative timing diagrams for each instruction are included in figures 4 through 25. all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase must complete on a byte boundary (cs driven high after a full 8-bits have been clocked) otherwise the instruction will be terminated. this feature further protects the device from inadvertent writes. additionally, while the memory is being programmed or erased, or when the status register is being written, all instructi ons except for read status register will be ignored until the program or erase cycle has completed. 7.2.1 manufacturer and device identification manufacturer id (m7-m0) winbond serial flash efh device id (id7-id0) (id15-id0) instruction abh, 90h, 92h 9fh w25x40bl 12h 3013h
w25x40bl - 14 - 7.2.2 instruction set (1) instruction name byte 1 code byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes write enable 06h write disable 04h write enable for volatile status register 50h read status register 05h (s7?s0) (1) (2) write status register 01h s7?s0 read data 03h a23?a16 a15?a8 a7?a0 (d7?d0) (next byte) continuous fast read 0bh a23?a16 a15?a8 a7?a0 dummy (d7?d0) (next byte) continuous fast read dual output 3bh a23?a16 a15?a8 a7?a0 dummy (d7-d0, ?) (5) (one byte per 4 clocks, continuous) fast read dual i/o bbh a23-a8 (6) a7-a0, m7- m0 (6) (d7-d0, ?) (5) page program 02h a23?a16 a15?a8 a7?a0 (d7?d0) (next byte) up to 256 bytes sector erase (4kb) 20h a23?a16 a15?a8 a7?a0 block erase (32kb) 52h a23?a16 a15?a8 a7?a0 block erase (64kb) d8h a23?a16 a15?a8 a7?a0 chip erase c7h/60h power-down b9h release power-down / device id abh dummy dummy dummy (id7-id0) (4) manufacturer/ device id (3) 90h dummy dummy 00h (m7-m0) (id7-id0) manufacturer/device id by dual i/o 92h a23-a8 a7-a0, m[7:0] (mf[7:0], id[7:0]) jedec id 9fh (m7-m0) manufacturer (id15-id8) memory type (id7-id0) capacity read unique id 4bh dummy dummy dummy dummy (id63-id0) read unique id notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ?( )? indicate data being read from the device on the do pin. 2. the status register contents will repeat cont inuously until /cs terminates the instruction. 3. see manufacturer and device identification table for device id information. 4. the device id will repeat continuously until /cs terminates the instruction. 5. dual output and dual i/o data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 6. dual input address io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1
w25x40bl publication release date: april 21, 2011 - 15 - preliminary - revision b 0 do (io 1 ) 7.2.3 write enable (06h) the write enable instruction (figure 4) sets the writ e enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page program, sector erase, block erase, chip erase and write status register instruction. the write enable instruction is entered by driving /cs low, shifting the instruction code ?06h? into the data input (di) pin on the rising edge of clk, and then driving /cs high. /cs clk di (io ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (06h) high impedance figure 4. write enable instruction sequence diagram 7.2.4 write enable for volatile status register (50h) the non-volatile status register bits described in secti on 7.1 can also be written to as volatile bits. this gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the status register non-volatile bits. to write the volatile values into the status register bits, the write enable for volatile status register (50h) instruction must be issued prior to a write status register (01h) instruction. write enable for volatile status register instruction (figure 5) will not set the write enable latch (wel) bit, it is only valid for the write status register instruction to change the volatile status register bit values. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (50h) high impedance figure 5. write enable for volatile status register instruction sequence diagram
w25x40bl - 16 - 0 do (io 1 ) 7.2.5 write disable (04h) the write disable instruction (figure 6) resets the write enable latch (wel) bit in the status register to a 0. the write disable instruction is entered by driving /cs low, shifting the instruction code ?04h? into the dio pin and then driving /cs high. note that the wel bit is automatically reset after power-up and upon completion of the write status register, page program, sector erase, block erase and chip erase instructions. /cs clk di (io ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (04h) high impedance figure 6. write disable instruction sequence diagram
w25x40bl publication release date: april 21, 2011 - 17 - preliminary - revision b do (io 1 ) 7.2.6 read status register (05h) the read status register instruction allows the 8-bit status register to be read. the instruction is entered by driving /cs low and shifting the instruction code ?05h? into the dio pin on the rising edge of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 7. the status register bits are shown in figure 3 and include the busy, wel, bp2-bp0, tb and srp bits (see description of the status register earlier in this datasheet). the status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. the status register can be read continuously, as shown in figure 7. the instruction is completed by driving /cs high. /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (05h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 status register out status register out ** = msb * figure 7. read status register instruction sequence diagram 7.2.7 write status register (01h) the write status register instruction allows the stat us register to be written. only non-volatile status register bits srp, tb, bp2, bp1, bp0 (bits 7 thru 2 of status register) can be written to. all other status register bit locations are read-only and will not be affected by the write status register instruction. the status register bits are shown in figure 3 and described in 7.1. to write non-volatile status register bits, a standard write enable (06h) instruction must previously have been executed for the device to accept the write st atus register instruction (status register bit wel must equal 1). once write enabled, the instruction is entered by driving /cs low, sending the instruction code ?01h?, and then writing the status register data byte as illustrated in figure 8. to write volatile status register bits, a write enable for volatile status register (50h) instruction must have been executed prior to the write status register instruction (status register bit wel remains 0). upon power off, the volatile status register bit va lues will be lost, and the non-volatile status register bit values will be restored when power on again. to complete the write status register instruction, the /cs pin must be driven high after the eighth bit of data that is clocked in. if this is not done the write status register instruction will not be executed.
w25x40bl during non-volatile status register write operation (06h combined with 01h), after /cs is driven high, the self-timed write status register cycle will commence for a time duration of t w (see ac characteristics). while the write status register cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to accept other instructions again. after the write status register cycle has finished, the write enable latch (wel) bit in the status register will be cleared to 0. during volatile status register write operation (50h combined with 01h), after /cs is driven high, the status register bits will be refreshed to the new values within the time period of t shsl2 (see ac characteristics). busy bit will remain 0 during the status register bit refresh period. please refer to 7.1 for detailed status register bit descriptions. factory default for all status register bits are 0. figure 8. write status register instruction sequence diagram - 18 -
w25x40bl publication release date: april 21, 2011 - 19 - preliminary - revision b do (io 1 ) 7.2.8 read data (03h) the read data instruction allows one more data bytes to be sequentially read from the memory. the instruction is initiated by driving the /cs pin low and then shifting the instruction code ?03h? followed by a 24-bit address (a23-a0) into the dio pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is completed by driving /cs high. the read data instruction sequence is shown in figure 9. if a read data instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read data instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (03h) 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 high impedance 7 6 5 4 3 2 1 0 7 24-bit address 23 22 21 3 2 1 0 data out 1 * * = msb * figure 9. read data instruction sequence diagram
w25x40bl - 20 - 7.2.9 fast read (0bh) the fast read instruction is similar to the read data instruction except that it can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 10. the dummy clocks allow the devices internal circuits additional time for setting up the initial address. during the dummy clocks the data value on the dio pin is a ?don?t care?. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (0bh) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 (io 0 ) do (io 1 ) * /cs clk di 32 33 34 35 36 37 38 39 dummy clocks 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 high impedance 7 6 5 4 3 2 1 0 7 43 31 data out 2 * 7 6 5 4 3 2 1 0 * 0 = msb * figure 10. fast read instruction sequence diagram
w25x40bl publication release date: april 21, 2011 - 21 - preliminary - revision b 7.2.10 fast read dual output (3bh) the fast read dual output (3bh) instruction is similar to the standard fast read (0bh) instruction except that data is output on two pins, do and dio, instead of just do. this allows data to be transferred from the w25x40bl at twice the rate of standard spi devices. the fast read dual output instruction is ideal for quickly downloading code fr om flash to ram upon power-up or for applications that cache code-segments to ram for execution. similar to the fast read instruction, the fast r ead dual output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 11. the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input data during the dummy clocks is ?don?t care?. however, the dio pin should be high-impedance prior to the falling edge of the first data out clock. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (3bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 6 4 2 0 24-bit address 23 22 21 3 2 1 0 * * 31 31 /cs clk di (io 0 ) do (io 1 ) dummy clocks 0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 7 5 3 1 6 4 2 0 6 4 2 0 6 4 2 0 high impedance 7 5 3 1 7 5 3 1 7 5 3 1 io 0 switches from input to output 6 7 data out 1 * data out 2 * data out 3 * data out 4 = msb * figure 11. fast read dual output instruction sequence diagram
w25x40bl - 22 - 7.2.11 fast read dual i/o (bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two io pins, io 0 and io 1 . it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits (a23-0) two bits per cloc k. this reduced instruction overhead may allow for c ode execution (xip) directly from the dual spi in some applications. fast read dual i/o with ?continuous read mode? the fast read dual i/o instruction can further reduce instruction overhead through setting the ?continuous read mode? bits (m7-0) after the input address bits (a23-0), as shown in figure 12a. the upper nibble of the (m7-4) controls the length of the next fast read dual i/o instruction through the inclusion or exclusion of the first byte instructi on code. the lower nibble bits of the (m3-0) are don?t care (?x?). however, the io pins should be high-impedance prior to the falling edge of the first data out clock. if the ?continuous read mode? bits m5-4 = (1,0), then the next fast read dual i/o instruction (after /cs is raised and then lowered) does not require the bbh instruction code, as shown in figure 12b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the ?continuous read mode? bits m5-4 do not equal to (1,0), the next instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a ?continuous read mode? reset instruction can also be used to reset (m7-0) before issuing normal instructions (see 7.2.13 for detail descriptions). /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (bbh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 23 /cs clk di (io 0 ) do (io 1 ) 0 32 33 34 35 36 37 38 39 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 ** ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 22 19 23 1 a23-16 a15-8 a7-0 m7-0 b y t e 1b y t e 2b y t e 3b y t e 4 = msb * * figure 12a. fast read dual i/o instruction sequence (initial instruction or previous m5-4 10)
w25x40bl publication release date: april 21, 2011 - 23 - preliminary - revision b /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 8 9 10 11 12 13 14 15 24 25 26 27 28 29 30 31 6 4 2 0 * * 15 /cs clk di (io 0 ) do (io 1 ) 0 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 ** ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 a23-16 a15-8 a7-0 m7-0 b y t e 1b y t e 2b y t e 3b y t e 4 01234567 16 17 18 20 21 22 19 23 * = msb * 1 figure 12b. fast read dual i/o instruction sequence (previous instruction set m5-4 = 10)
w25x40bl - 24 - 7.2.12 continuous read mode bits (m7-0) the ?continuous read mode? bits are used in conjunction with the ?fast read dual i/o? instruction to provide the highest random flash memory access rate with minimum spi instruction overhead, thus allow true xip (execute in place) to be performed on serial flash devices. m7-0 need to be set by the dual i/o read instruction. m5-4 are used to control whether the 8-bit spi instruction code bbh is needed or not for the next command. when m5-4 = (1,0), the next command will be treated same as the current dual i/o read command without needing the 8-bit instruction code; when m5-4 do not equal to (1,0), the device returns to normal spi mode, all commands can be accepted. m7-6 and m3-0 are reserved bits for future use, either 0 or 1 values can be used. 7.2.13 continuous read mode reset (ffffh) continuous read mode reset instruction can be used to set m4 = 1, thus the device will release the continuous read mode and return to normal spi operation, as shown in figure 13. 11 02 /cs mode 0 mode 3 4 6 8 10 12 mode 0 mode 3 clk io 0 io mode bit reset for dual i/o don?t care ffffh /cs mode 0 mode 3 clk io 0 io don?t care 135791113 14 15 figure 13. continuous read mode reset for fast read dual i/o since w25x40bl does not have a hardware reset pin, so if the controller resets while w25x40bl is set to continuous mode read, the w25x40bl will not recognize any initial standard spi instructions from the controller. to address this possibility, it is recommended to issue a continuous read mode reset instruction as the first instruction after a system reset. doing so will release the device from the continuous read mode and allow standard spi instructions to be recognized. to reset ?continuous read mode? during dual i/o operation, sixteen clocks are needed to shift in instruction ?ffffh?.
w25x40bl publication release date: april 21, 2011 - 25 - preliminary - revision b 7.2.14 page program (02h) the page program instruction allows up to 256 bytes of data to be programmed at previously erased to all 1s (ffh) memory locations. a write enable instruction must be executed before the device will accept the page program instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code ?02h? followed by a 24-bit address (a23-a0) and at least one data byte, into the dio pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. one condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page program instruction will not be executed. after /cs is driven high, the self-timed page program instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the page program cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the page program instruction will not be executed if the addressed page is protected by the block protect (bp2, bp1, and bp0) bits (see status register memory protection table). /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (02h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk 40 di (io 0 ) 41 42 43 44 45 46 47 48 49 50 52 53 54 55 2072 51 39 data byte 2 7 6 5 4 3 2 1 0 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 3 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb * figure 14. page program instruction sequence diagram
w25x40bl - 26 - (io 1 ) 7.2.15 4kb sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k-bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the sector erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?20h? followed a 24-bit sector address (a23-a0) (see figure 2). the sector erase instruction sequence is shown in figure 15. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction will not be executed. after /cs is driven high, the self-timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase instruction will not be executed if the addressed page is protected by the block protect (tb, bp2, bp1, and bp0) bits (see status register memory protection table). /cs clk di (io 0 ) do mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (20h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb * figure 15. sector erase instruction sequence diagram
w25x40bl publication release date: april 21, 2011 - 27 - preliminary - revision b 0 do (io 1 ) 7.2.16 32kb block erase (52h) the block erase instruction sets all memory within a specified block (32k-bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?52h? followed a 24-bit block address (a23-a0) (see figure 2). the block erase instruction sequence is shown in figure 16. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self-timed block erase instruction will commence for a time duration of t be 1 (see ac characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect (sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). /cs clk di (io ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (52h) 8 9 29 30 31 24-bit address 23 22 2 1 0 high impedance * mode 0 mode 3 = msb * figure 16. 32kb block erase instruction sequence diagram
w25x40bl - 28 - do (io 1 ) 7.2.17 64kb block erase (d8h) the block erase instruction sets all memory within a specified block (64k-bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?d8h? followed a 24-bit block address (a23-a0) (see figure 2). the block erase instruction sequence is shown in figure 17. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self-timed block erase instruction will commence for a time duration of t be (see ac characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect (tb, bp2, bp1, and bp0) bits (see status register memory protection table). /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (d8h) 8 9 29 30 31 24-bit address 23 22 2 1 0 high impedance * mode 0 mode 3 = msb * figure 17. block erase instruction sequence diagram
w25x40bl publication release date: april 21, 2011 - 29 - preliminary - revision b do (io 1 ) 7.2.18 chip erase (c7h or 60h) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instru ction is initiated by driving the /cs pin low and shifting the instruction code ?c7h? or ?60h?. the chip erase instruction sequence is shown in figure 18. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driven high, the self-timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. after the chip erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any page is protected by the block protect (bp2, bp1, and bp0) bits (see status register memory protection table). /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (c7h/ 60h) high impedance figure 18. chip erase instruction sequence diagram
w25x40bl - 30 - 7.2.19 power-down (b9h) although the standby current during normal operation is relatively low, standby current can be further reduced with the power-down instruction. the lower power consumption makes the power-down instruction especially useful for battery powered applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by dr iving the /cs pin low and shifting the instruction code ?b9h? as shown in figure 19. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the power- down instruction will not be executed. after /cs is driven high, the power-down state will entered within the time duration of t dp (see ac characteristics). while in the power-down state only the release from power-down / device id instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. the device always powers-up in the normal operation with the standby current of icc1. /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (b9h) mode 0 mode 3 tdp power-down current stand-by current figure 19. deep power-down instruction sequence diagram
w25x40bl publication release date: april 21, 2011 - 31 - preliminary - revision b 7.2.20 release power-down / device id (abh) the release from power-down / device id instruction is a multi-purpose instruction. it can be used to release the device from the power-down state, obtai n the devices electronic identification (id) number or do both. when used only to release the device from the power- down state, the instruction is issued by driving the /cs pin low, shifting the instruction code ?abh? and driving /cs high as shown in figure 20. after the time duration of t res1 (see ac characteristics) the device will resume normal operation and other instructions will be accepted. the /cs pin must remain high during the t res1 time duration. when used only to obtain the device id while not in t he power-down state, the instruction is initiated by driving the /cs pin low and shifting the instruction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 20. the device id value for the w25x40bl is listed in manufacturer and device identification table. the device id can be read continuously. the instruction is completed by driving /cs high. when used to release the device from the power-down state and obtain the device id, the instruction is the same as previously described, and shown in figure 21, except that after /cs is driven high it must remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions will be accepted. if the release from power-down / device id instruction is issued while an erase, program or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) mode 0 mode 3 tres1 power-down current stand-by current figure 20. release power-down instruction sequence
w25x40bl - 32 - tres2 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) high impedance 8 9 29 30 31 3 dummy bytes 23 22 2 1 0 * mode 0 mode 3 7 6 5 4 3 2 1 0 * 32 33 34 35 36 37 38 device id power-down current = msb * stand-by current figure 21. release power-down / device id instruction sequence diagram
w25x40bl publication release date: april 21, 2011 - 33 - preliminary - revision b 7.2.21 read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power-down/ device id instruction that provides both jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code ?90h? followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 22. the device id value for the w25x40bl is listed in manufacturer and device identification table. if the 24-bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (90h) high impedance 8 9 10 28 29 30 31 address (000000h) 23 22 21 3 2 1 0 device id (io 1 ) * /cs clk di (io 0 ) do 32 33 34 35 36 37 38 39 40 41 42 44 45 46 7 6 5 4 3 2 1 0 * manufacturer id (efh) 43 31 0 mode 0 mode 3 = msb * figure 22. read manufacturer / device id diagram
w25x40bl - 34 - 7.2.22 read manufacturer / device id dual i/o (92h) the manufacturer / device id dual i/o instruction is an alternative to the read manufacturer/device id instruction that provides both the jedec assigned manufacturer id and the specific device id at 2x speed. the read manufacturer / device id dual i/o instruction is similar to the fast read dual i/o instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code ?92h? followed by a 24-bit address (a23-a0) of 000000h, but with the capability to input the address bits two bits per clock. after which, the manufacturer id for winbond (efh) and the device id are shifted out 2 bits per clock on the falling edge of clk with most significant bits (msb) first as shown in figure 23. the device id value for the w25x40bl is listed in manufacturer and device identification table. if the 24-bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (92h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 7 5 3 1 ** 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 23 ** a23-16 a15-8 a7-0 (00h) m7-0 /cs clk di (io 0 ) 24 do (io 1 ) 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 0 mode 0 mode 3 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 0 1 ios switch from input to output mfr id device id mfr id (repeat) device id (repeat) ** ** = msb * figure 23. read manufacturer / device id dual i/o diagram note: the ?continuous read mode? bits m7-0 must be set to fxh to be compatible with fast read dual i/o instruction.
w25x40bl publication release date: april 21, 2011 - 35 - preliminary - revision b 7.2.23 read unique id number (4bh) the read unique id number instruction accesses a factory-set read-only 64-bit number that is unique to each w25x40bl device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the read unique id instruction is initiated by driving the /cs pin low and shifting the instruction code ?4bh? followed by a four bytes of dummy clocks. after which, the 64-bit id is shifted out on the falling edge of clk as shown in figure 24. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (4bh) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 /cs clk di 24 (io 0 ) do (io 1 ) 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 mode 0 mode 3 dummy byte 1 dummy byte 2 39 40 41 42 dummy byte 3 dummy byte 4 * 63 62 61 2 100 101 102 1 0 high impedance 64-bit unique serial number = msb * figure 24. read unique id number instruction sequence
w25x40bl - 36 - 7.2.24 jedec id (9fh) for compatibility reasons, the w25x40bl provides several instructions to electronically determine the identity of the device. the read jedec id instruction is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003. the instruction is initiated by driving the /cs pin low and shifting the instruction code ?9fh?. the jedec assigned manufacturer id byte for winbond (efh) and two device id bytes, memory type (id15-id8) and capacity (id7-id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 25. for memory type and capacity values refer to manufacturer and device identification table. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (9fh) high impedance 8 9 10 12 13 14 15 capacity id7-0 /cs clk di (io 0 ) do 16 (io 1 ) 17 18 19 20 21 22 23 manufacturer id (efh) 24 25 26 28 29 30 7 6 5 4 3 2 1 0 * 27 15 mode 0 mode 3 11 7 6 5 4 3 2 1 0 * memory type id15-8 = msb * figure 25. read jedec id
w25x40bl publication release date: april 21, 2011 - 37 - preliminary - revision b 8. electrical characteristics (1) 8.1 absolute maximum ratings (2) parameters symbol conditions range unit supply voltage vcc ?0.6 to +4.6 v voltage applied to any pin v io relative to ground ?0.6 to vcc +0.4 v transient voltage on any pin v iot <20ns transient relative to ground ?2.0v to vcc+2.0v v storage temperature t stg ?65 to +150 c lead temperature t lead see note (3) c electrostatic discharge voltage v esd human body model (4) ?2000 to +2000 v notes: 1. specification for the w25x40bl is preliminary. see preliminary designation at the end of this document. 2. this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device reliability. exposure beyond absolute maximum ratings may cause permanent damage. 3. compliant with jedec standard j-std-20c for small body sn-pb or pb-free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 4. jedec std jesd22-a114a (c1=100 pf, r1=1500 ohms, r2=500 ohms). 8.2 operating ranges parameter symbol conditions spec unit min max supply voltage (1) vcc f r = 50mhz, f r = 25mhz 2.3 3.6 v f r = 80mhz, f r = 50mhz 2.7 3.6 f r = 104mhz, f r = 50mhz 3.0 3.6 ambient temperature, operating t a industrial ?40 +85 c note: 1. vcc voltage during read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage.
w25x40bl - 38 - 8.3 power-up timing and write inhibit threshold parameter symbol spec unit min max vcc (min) to /cs low t vsl (1) 10 s time delay before write instruction t puw (1) 1 10 ms write inhibit threshold voltage v wi (1) 1 2 v note: 1. these parameters are characterized only. vcc tvsl read instructions allowed device is fully accessible tpuw /cs must track vcc program, erase and write instructions are ignored reset state vcc (max) vcc (min) v wi time figure 26. power-up timing and voltage levels
w25x40bl publication release date: april 21, 2011 - 39 - preliminary - revision b 8.4 dc electrical characteristics parameter symbol conditions spec unit min typ max input capacitance c in (1) v in = 0v (1) 6 pf output capacitance cout (1) v out = 0v (1) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 25 50 a power-down current i cc 2 /cs = vcc, vin = gnd or vcc 1 5 a current read data / dual 1mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 4/5 6/7.5 ma current read data / dual 33mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 6/7 9/10.5 ma current read data / dual output read 50mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 7/8 10/12 ma current read data / dual output read 80mhz (2, 3) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 10/11 15/16.5 ma current write status register i cc 4 /cs = vcc 8 12 ma current page program i cc 5 /cs = vcc 20 25 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i cc 7 /cs = vcc 20 25 ma input low voltage v il vcc x 0.3 v input high voltage v ih vcc x 0.7 v output low voltage v ol i ol = 100 a 0.2 v output high voltage v oh i oh = ?100 a vcc ? 0.2 v notes: 1. tested on sample basis and specified through design and characterization data. ta = 25 c, vcc = 3v. 2. checker board pattern. 3. the voltage range for 80mhz operation is 2.7v to 3.6v.
w25x40bl - 40 - 8.5 ac measurement conditions parameter symbol spec unit min max load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.2 vcc to 0.8 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0.5 vcc to 0.5 vcc v note: 1. output hi-z is defined as the point where data out is no longer driven. i timi input levels 0.8 vcc nput and output ng reference levels 0.2 vcc 0.5 vcc figure 27. ac measurement i/o waveform
w25x40bl publication release date: april 21, 2011 - 41 - preliminary - revision b 8.6 ac electrical characteristics (2.3~3.6v) description symbol alt spec unit min typ max clock frequency for all instructions, except read data (03h) 2.3v-3.6v vcc & industrial temperature f r f c d.c. 50 mhz clock freq. read data instruction 03h f r d.c. 25 mhz clock high, low time, for fast read (0bh, 3bh) / other instructions except read data (03h) t clh , t cll (1) 6 ns clock high, low time for read data (03h) instruction t crlh , t crll (1) 8 ns clock rise time peak to peak t clch (2) 0.1 v/ns clock fall time peak to peak t chcl (2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns /cs active hold time relative to clk t chsh 5 ns /cs not active setup time relative to clk t shch 5 ns /cs deselect time (for array read ? array read) t shsl 1 t csh 10 ns /cs deselect time (f or erase or program ? read status registers and volatile status register write) t shsl 2 t csh 100 ns output disable time t shqz (2) t dis 7 ns clock low to output valid t clqv t v 9 ns output hold time t clqx t ho 0 ns continued ? next page
w25x40bl - 42 - ac electrical characteristics (2.3~3.6v) (cont?d) description symbol alt spec unit min typ max /hold active setup time relative to clk t hlch 5 ns /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns /hold to output low-z t hhqx (2) t lz 7 ns /hold to output high-z t hlqz (2) t hz 12 ns write protect setup time before /cs low t whsl (3) 20 ns write protect hold time after /cs high t shwl (3) 100 ns /cs high to power-down mode t dp (2) 3 s /cs high to standby mode without electronic signature read t res 1 (2) 3 s /cs high to standby mode with electronic signature read t res 2 (2) 1.8 s write status register time t w 10 15 ms byte program time (first byte) (4) t bp1 30 50 s additional byte program time (after first byte) (4) t bp2 2.5 12 s page program time t pp 1 3 ms sector erase time (4kb) t se 50 200/400 (5) ms block erase time (32kb) t be 1 180 800 ms block erase time (64kb) t be 2 200 1,000 ms chip erase time t ce 1.5 4 s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or characterization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when srp is set to 1. 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed. 5. max value t se with <50k cycles is 200ms and >50k & <100k cycles is 400ms.
w25x40bl publication release date: april 21, 2011 - 43 - preliminary - revision b 8.7 ac electrical characteristics (2.7~3.6v) description symbol alt spec unit min typ max clock frequency for all instructions except read data instruction (03h) 2.7v-3.6v vcc & industrial temperature f r f c d.c. 80 mhz clock frequency for all instructions except read data instruction (03h) 3.0v-3.6v vcc & industrial temperature f r f c d.c. 104 mhz clock frequency for read data instruction (03h) f r d.c. 50 mhz clock high, low time for all instructions except read data (03h) t clh 1 , t cll 1 (1) 4 ns clock high, low time for read data (03h) instruction t crlh , t crll (1) 8 ns clock rise time peak to peak t clch (2) 0.1 v/ns clock fall time peak to peak t chcl (2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns /cs active hold time relative to clk t chsh 5 ns /cs not active setup time relative to clk t shch 5 ns /cs deselect time (for array read ? array read) t shsl 1 t csh 10 ns /cs deselect time (f or erase or program ? read status registers) volatile status register write time t shsl 2 t csh 50 50 ns output disable time t shqz (2) t dis 7 ns clock low to output valid t clqv 1 t v 1 7 ns clock low to output valid (for read id instructions) t clqv 2 t v 2 7.5 ns output hold time t clqx t ho 0 ns /hold active setup time relative to clk t hlch 5 ns continued ? next page
w25x40bl - 44 - ac electrical characteristics (2.7~3.6v) (cont?d) description symbol alt spec unit min typ max /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns /hold to output low-z t hhqx (2) t lz 7 ns /hold to output high-z t hlqz (2) t hz 12 ns write protect setup time before /cs low t whsl (3) 20 ns write protect hold time after /cs high t shwl (3) 100 ns /cs high to power-down mode t dp (2) 3 s /cs high to standby mode without electronic signature read t res 1 (2) 3 s /cs high to standby mode with electronic signature read t res 2 (2) 1.8 s write status register time t w 10 15 ms byte program time (first byte) (4) t bp1 20 50 s additional byte program ti me (after first byte) (4) t bp2 2.5 12 s page program time t pp 0.7 3.0 ms sector erase time (4kb) t se 30 200/400 (5) ms block erase time (32kb) t be 1 120 800 ms block erase time (64kb) t be 2 150 1,000 ms chip erase time t ce 1 4 s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or characterization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when srp0 bit is set to 1. 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed. 5. max value t se with <50k cycles is 200ms and >50k & <100k cycles is 400ms.
w25x40bl publication release date: april 21, 2011 - 45 - preliminary - revision b /cs clk io output 8.8 serial output timing tclqx tclqv tclqx tclqv tshqz tcll lsb out tclh msb out 8.9 serial input timing /cs clk io input tchsl msb in tslch tdvch tchdx tshch tchsh tclch tchcl lsb in tshsl 8.10 hold timing /cs clk io output /hold tchhl thlch tchhh thhch thlqz thhqx io input 8.11 write protect timing /cs clk /wp twhsl tshwl io input write status register is allowed write status register is not allowed
w25x40bl - 46 - 9. package specification 9.1 8-pin soic 150-mil (package code sn) l o c d a1 a e b seating plane y 0.25 gauge plane e h e 1 8 5 4 symbol millimeters inches min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.008 0.010 e ( 3 ) 3.80 4.00 0.150 0.157 d ( 3 ) 4.80 5.00 0.188 0.196 e ( 2 ) 1.27 bsc 0.050 bsc h e 5.80 6.20 0.228 0.244 y ( 4 ) - 0.10 - 0.004 l 0.40 1.27 0.016 0.050 t 0 10 0 10 notes: 1. controlling dimensions: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads coplanarity with respect to seating plane shall be within 0.004 inches .
w25x40bl publication release date: april 21, 2011 - 47 - preliminary - revision b 9.2 8-pin vsop 150-mil (package code sv) symbol millimeters inches min nom max min nom max a --- --- 1.00 --- --- 0.039 a1 0.05 0.10 0.15 0.002 0.004 0.006 a2 0.75 0.80 0.85 0.030 0.031 0.033 q 0.19 0.20 0.21 0.0075 0.0079 0.0083 b 0.33 --- 0.51 0.013 --- 0.020 c 0.125 bsc 0.005 bsc d 4.80 4.90 5.00 0.189 0.193 0.197 e 5.80 6.00 6.20 0.228 0.236 0.244 e1 3.80 3.90 4.00 0.150 0.154 0.157 e 1.27 bsc. 0.050 bsc. l 0.40 0.71 1.27 0.016 0.028 0.050 0 --- 10 0 --- 10
w25x40bl - 48 - 9.3 8-pin soic 208-mil (package code ss) symbol millimeters inches min nom max min nom max a 1.75 1.95 2.16 0.069 0.077 0.085 a1 0.05 0.15 0.25 0.002 0.006 0.010 a2 1.70 1.80 1.91 0.067 0.071 0.075 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.19 0.20 0.25 0.007 0.008 0.010 d 5.18 5.28 5.38 0.204 0.208 0.212 d1 5.13 5.23 5.33 0.202 0.206 0.210 e 5.18 5.28 5.38 0.204 0.208 0.212 e1 5.13 5.23 5.33 0.202 0.206 0.210 e 1.27 bsc 0.050 bsc h 7.70 7.90 8.10 0.303 0.311 0.319 l 0.50 0.65 0.80 0.020 0.026 0.031 y - - 0.10 - - 0.004 0 - 8 0 - 8 notes: 1. controlling dimensions: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d1 and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads coplanarity with respect to seating plane shall be within 0.004 inches .
w25x40bl publication release date: april 21, 2011 - 49 - preliminary - revision b seating plane 9.4 8-pin pdip 300-mil (package code da) 1 e d 1 b b e a 2 a c e base plane 1 a 1 e l a s 8 5 1 4 symbol millimeters inches min typ. max min typ. max a --- --- 4.45 --- --- 0.175 a1 0.25 --- --- 0.010 --- --- a2 3.18 3.30 3.43 0.125 0.130 0.135 b 0.41 0.46 0.56 0.016 0.018 0.022 b1 1.47 1.52 1.63 0.058 0.060 0.064 c 0.20 0.25 0.36 0.008 0.010 0.014 d - 9.14 9.65 - 0.360 0.380 e 7.37 7.62 7.87 0.290 0.300 0.310 e1 6.22 6.35 6.48 0.245 0.250 0.255 e1 2.29 2.54 2.79 0.090 0.100 0.110 l 3.05 3.30 3.56 0.120 0.130 0.140 . 0 - 15 0 - 15 e a 8.51 9.02 9.53 0.335 0.355 0.375 s --- --- 1.14 --- --- 0.045
w25x40bl - 50 - 9.5 8-pad uson 2x3-mm (package code ux) note: exposed pad dimension d2 & e2 may be different by die size. symbo l millimeter inches min typ. max min typ. max a 0.50 0.55 0.60 0.020 0.022 0.024 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.20 0.25 0.30 0.008 0.010 0.012 c D 0.15 ref D D 0.006 D d 1.90 2.00 2.10 0.075 0.079 0.083 d2 1.55 1.60 1.65 0.061 0.063 0.065 e 2.90 3.00 3.10 0.114 0.118 0.122 e2 0.15 0.20 0.25 0.006 0.008 0.010 e D 0.50 D D 0.020 D l 0.40 0.45 0.50 0.016 0.018 0.020 l1 D 0.10 D D 0.004 D l3 0.30 0.35 0.40 0.012 0.014 0.016 y 0.000 D 0.075 0.000 D 0.003 a pin 1 indent l1 a1 d e y d2 l3 e2 e b l c
w25x40bl publication release date: april 21, 2011 - 51 - preliminary - revision b 9.6 8-contact 6x5mm wson (package code zp) symbol millimeters inches min typ. max min typ. max a 0.70 0.75 0.80 0.0275 0.0295 0.0314 a1 0.00 0.02 0.05 0.0000 0.0007 0.0019 b 0.35 0.40 0.48 0.0137 0.0157 0.0188 c - 0.20 ref. - - 0.0078 ref. - d 5.90 6.00 6.10 0.2322 0.2362 0.2401 d2 3.35 3.40 3.45 0.1318 0.1338 0.1358 e 4.90 5.00 5.10 0.1929 0.1968 0.2007 e2 4.25 4.30 4.35 0.1673 0.1692 0.1712 e (2 ) 1.27 bsc 0.0500 bsc l 0.55 0.60 0.65 0.0216 0.0236 0.0255 y 0.00 - 0.075 0.0000 - 0.0029
w25x40bl - 52 - 8-pad wson 6x5mm cont?d. symbol millimeters inches min typ. max min typ. max solder pattern m 3.40 0.1338 n 4.30 0.1692 p 6.00 0.2360 q 0.50 0.0196 r 0.75 0.0255 notes: 1. advanced packaging information; please contact winbond for the latest minimum and maximum specifications. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package. 4. the metal pad area on the bottom center of the package is connected to the device ground (gnd pin). avoid placement of exposed pcb vias under the pad.
w25x40bl publication release date: april 21, 2011 - 53 - preliminary - revision b 10. ordering information (1) w 25x 40b l x x (2) w = winbond 25x = spiflash serial flash memory with 4kb sectors, dual outputs 40b = 4m-bit l = 2.3v to 3.6v sn = 8-pin soic 150-mil zp = 8-pad wson 6x5mm da = 8-pin pdip 300mil sv = 8-pin vsop 150-mil ss = 8 pin soic 208-mil ux = 8-pad uson 2x3mm i = industrial (-40c to +85c) g = green package (lead-free, rohs compliant, halogen-free (tbba), antimony-oxide-free sb 2 o 3 ) notes: 1a. standard bulk shipments are in tube (shape e). please specify alternate packing method, such as tape and reel (shape t) or tray (shape s), when placing orders. 1b. the ?w? prefix is not included on the part marking. 2. only the 2 nd letter is used for the part marking, package type zp is not used for the part marking. wson package type zp is not used for part marking. uson package type ux has special top marking due to size limitation.
w25x40bl - 54 - 10.1 valid part numbers and top side marking the following table provides the valid part numbers for the w25x40bl spiflash memories. please contact winbond for specific availability by density and package type. winbond spiflash memories use a 12-digit product number for ordering. however, due to limited space, the top side marking on all packages uses an abbreviated 10-digit number. package type density product number top side marking sn soic-8 150mil 4m-bit w25x40blsnig 25x40blnig sv vsop-8 150mil 4m-bit W25X40BLSVIG 25x40blvig ss soic-8 208mil 4m-bit w25x40blssig 25x40blsig ux (2) uson-8 2x3mm 4m-bit w25x40bluxig 4axxx 0gxxxx zp (1) wson-8 6x5mm 4m-bit w25x40blzpig 25x40blig da pdip-8 300mil 4m-bit w25x40bldaig 25x40blaig notes: 1. for wson packages, the package type zp is not used in the top side marking. 2. uson package type ux has special top marking due to size limitation. 4 = 4m-bits; a = w25x series, 2.5v; 0 = standard product, g = green package.
w25x40bl publication release date: april 21, 2011 - 55 - preliminary - revision b 11. revision history version date page description a 10/14/09 all new create preliminary. b 04/21/11 37-44 47, 50 updated ac/dc parameters added uson, vsop packages preliminary designation the ?preliminary? designation on a winbond datasheet indicates that the product is not fully characterized. the specifications are subject to change and are not g ua ranteed. winbond or an authorized sales representative should be consulted for current information before using this product. trademarks winbond and spiflash are trademarks of winbond electronics corporation. all other marks are the property of their respective owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein pers onal injury, death or severe property or environmental damage could occur. winbond customers us ing or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. information in this document is provided solely in connection with winbond products. winbond reserves the right to make changes, corr ections, modifications or improvements to this document and the products and services described herein at any time, without notice.

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